Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach

• Published in: Journal of electronic testing Vol. 28; no. 6; pp. 777 - 789
• Main Authors: Portela-Garcia, M., Lindoso, A., Entrena, L., Garcia-Valderas, M., Lopez-Ongil, C., Marroni, N., Pianta, B., Bolzani Poehls, L., Vargas, F.
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01-12-2012; Springer Nature B.V
• Subjects: CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD; Electrical Engineering; Electronics; Engineering; Fault diagnosis; Fault tolerance; Faults; Microprocessors; Monitoring; Redundancy; Robustness; Signatures; Single Event Effects; Single event upsets; Software; Software-based fault tolerance techniques; SEU; SET; FPGA-based fault injection
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-012-5321-4

Nowadays, microprocessor-based system’s robustness under Single Event Effects (SEEs) represents a very important concern. A widely adopted solution to make a microprocessor-based system robust consists in modifying the application code by adding redundancy and fault tolerance capabilities. In this context, the main idea behind this paper is to evaluate a software-based technique named Optimized Embedded Signature Monitoring (OESM) using an FPGA-based fault injection technique, which is able to inject a high number of Single Event Upsets (SEUs) and Single Event Transients (SETs) in a short period of time. The obtained results demonstrated not only the increase of system’s robustness level, but also point out the remaining weak areas in the microprocessor-based system with respect to both types of SEEs.