A signed pulse-train-based image processor-array for parallel kernel convolution in vision sensors

• Published in: Sensor review Vol. 40; no. 4; pp. 521 - 528
• Main Authors: Danesh, Ahmad Reza, Habibi, Mehdi
• Format: Journal Article
• Language: English
• Published: Bradford Emerald Publishing Limited 21-07-2020; Emerald Group Publishing Limited
• Subjects: Array processors; Circuits; Convolution; Data compression; Edge detection; Error analysis; Field programmable gate arrays; High speed; Image detection; Image enhancement; Image filters; Image processing; Image quality; Kernels; Microprocessors; Power consumption; Pulse duration modulation; Quality control; Real time; Sensor arrays; Sensors; Sharpening; Signal processing; Signal to noise ratio; Smart sensors; Vision systems; Pulse width processing; Image processing; Parallel image processer; Image filtering; VLSI design; Sensors; Kernel convolution
• ISSN: 0260-2288; 1758-6828
• DOI: 10.1108/SR-10-2019-0242

Purpose
The purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement.
Design/methodology/approach
In this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number.
Findings
The performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented.
Originality/value
The presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values.