An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 59; no. 11; pp. 2481 - 2494
• Main Authors: Liangge Xu, Stadius, K., Ryynanen, J.
• Format: Journal Article
• Language: English
• Published: IEEE 01-11-2012
• Subjects: All-digital phase-locked loop (ADPLL); binary search; Calibration; frequency calibration; Frequency control; frequency synthesizer; Frequency synthesizers; phase digitization; Phase frequency detector; RF signals; Time frequency analysis; time-to-digital converter (TDC); variable phase accumulator (VPA)
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2012.2189055

This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it eliminates spurious tones associated with frequency reference retiming. In addition, the ADPLL employs an original frequency calibration technique that allows an extremely fine calibration resolution with minimized calibration time. Theoretical analysis is provided for both the architectural modification and frequency calibration technique. The ADPLL has been implemented in a 65-nm CMOS. Its simulation and measurement results are presented.