Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 8; pp. 1388 - 1397
• Main Author: Feng, Zhuo
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-08-2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Current distribution; Design. Technologies. Operation analysis. Testing; Electrical engineering. Electrical power engineering; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Integrated circuits; Linear programming; multilevel optimization; Optimization methods; Power electronics, power supplies; Power grids; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensitivity; Upper bound; vectorless method; Vectors; voltage integrity verification; Performance evaluation; Cell structure; multilevel optimization; vectorless method; voltage integrity verification; Lower bound; Scalability; Worst case method; Flip-chip; Integrated circuit design; Linear programming; Power supply; Power electronics; Algorithm; Optimization; Upper bound; Electrical network; Integrated circuit; Large scale; power grids; Multilevel system; Gain; Electrical characteristic
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2012.2212033

With the current aggressive integrated circuit technology scaling, vectorless power grid voltage integrity verification becomes key to designing reliable power delivery networks. To address the challenges of existing vectorless power grid verification methods that suffer from excessively long optimization time and poor scalability to large power grid designs, in this paper, we present a scalable multilevel vectorless power grid verification method which can efficiently tackle very large scale power grid verifications. By taking advantage of a series of coarsest to coarser grid verifications, the finest power grid verification can be accomplished in a more efficient way. To gain good efficiency, global and local "critical regions" for power grid verification are introduced, while power grid structure and electrical properties are exploited to facilitate identifying the worst case voltage drops across the entire chip. The proposed multilevel power grid verification algorithm allows more flexible tradeoffs between verification cost and solution quality, while providing the desired conservative upper/lower bounds for worst case voltage drops. Extensive experimental results show that our approach can efficiently handle very large power grid designs without sacrificing the final power grid verification accuracy. For example, finding the worst voltage drop for a flip-chip power grid design with one million nodes takes less than two hours.