Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 66; no. 5; pp. 753 - 757
• Main Authors: Sun, Yanan, Gu, Jiawei, He, Weifeng, Wang, Qin, Jing, Naifeng, Mao, Zhigang, Qian, Weikang, Jiang, Li
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: break-even time; Circuits; CMOS; Data storage; Energy; Energy efficiency; Energy storage; multi-level cell; Nonvolatile memory; Nonvolatile SRAM; Optimization; Power supplies; Rams; Random access memory; Resistance; restore energy; restore yield; RRAM; Short circuits; SRAM cells; Static random access memory; store energy; Switching circuits; Transistors
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2019.2908243

A new nonvolatile static random access memory (nvSRAM) design based on the multi-level cell (MLC) characteristics of resistive RAMs (RRAMs) is presented in this brief to reduce the store energy of frequent-off and instant-on applications. The data store circuitry is designed to enable the energy-efficient multi-bit data backup of every two SRAM cells into a single four-level MLC RRAM of the proposed MLC-nvSRAM cell. Precharging restore scheme is employed to reduce the restore energy by suppressing the short-circuit and leakage currents when power supply is ramping up for data restore. Optimization method of multiple resistance states is also developed to maximize the restore yield considering the CMOS and RRAM process variations. The store and restore energy of the proposed MLC-nvSRAM circuit are reduced by 53.97% and 62.61%, respectively, as compared to the lowest store and restore energy of the previously published nvSRAM circuits based on single-level cell (SLC) RRAMs.