Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 5; pp. 1993 - 1997
• Main Authors: Chung-Hsien Chang, Shi-Huang Chen, Bo-Wei Chen, Wen Ji, Bharanitharan, K., Jhing-Fa Wang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Computer architecture; Fixed-point system; Hardware; iterative design; Polynomials; Registers; Signal processing algorithms; Speech processing; Fixed-point system; speech processing; iterative design
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2477312

This brief presents a fixed-point architecture based on a reconfigurable scheme for integrating several commonly used mathematical operations of speech signal processing. The proposed design can perform two transcendental mathematical operations called logarithm and powering, and three commonly used computations with similar operations named polynomial calculation, filtering, and windowing. By analyzing the adopted algorithms of the above five operations, a simplified computing unit is designed. This unit can combine six types of operations by reconfiguring the data paths, and the same multiply-add architecture can be reused for reducing the redundant usage of logic gates. The experimental results reveal that the proposed design can work at a 200-MHz clock rate, and its gate count only has 11.9k. Compared with the results of the floating-point function, the median errors of the proposed design for computing the powering and logarithmic functions are 0.57% and 0.11%, respectively. Such results indicate that this simple architecture can be effectively used in most speech processing applications.