Analysis and Comparison of High-Resolution GS/s Samplers in Advanced BiCMOS and CMOS

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 65; no. 5; pp. 532 - 536
• Main Authors: Lal, Deeksha, Ali, Ahmed M. A., Ricketts, David S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 28nm CMOS; 90nm SiGe BiCMOS; ADC; Analog to digital converters; Bandwidth; BiCMOS integrated circuits; CMOS; CMOS technology; Distortion; HD3; High resolution; High speed; Millimeter waves; mmWave; sample and hold amplifier; sampler; Samplers; SFDR; SHA; Signal to noise ratio; switched-capacitor; Switching circuits; Wireless communication systems; Wireless communications
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2018.2822785

High-speed and high-resolution analog to digital converters (ADCs) (10+ bits) are essential components of modern wireless communication systems and mmWave radios. Their performance is often limited by the noise and distortion from the front-end samplers, the design of which can be challenging. Modern ADC design has moved heavily to scaled CMOS technologies due to its attractive digital and integration capabilities, but these processes face challenges of high fabrication costs, and diminishing analog performance that has to be bolstered by extensive digital calibration. On the other hand, BiCMOS processes have advanced and scaled sufficiently that they may be able to offer the best of the mixed signal world. This brief examines, both theoretically and through simulations, the design of samplers for high-speed, low-distortion in CMOS and BiCMOS for GS/s ADCs. Two fully differential samplers, with an equivalent sampling frequency of 5 GS/s and an input frequency range of up to 10 GHz, are designed in a 90-nm BiCMOS and a 28-nm CMOS process, respectively, and their distortion performance is analyzed, simulated, and compared.