Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 1; pp. 37 - 46
• Main Authors: Rezaei Khezeli, Maryam, Moaiyeri, Mohammad Hossein, Jalali, Ali
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bundling; Carbon; Carbon nanotubes; Circuits; CNTFETs; Delay; Electric power distribution; Field effect transistors; Integrated circuit interconnections; Interconnections; Multi wall carbon nanotubes; Multiple-valued logic (MVL); multiwalled carbon nanotube (MWCNT); Nodes; Noise; power interconnects; Rails; Resistance; RLC circuits; Semiconductor devices; simultaneous switching noise (SSN); Switching; Wires
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2869761

In this paper, the impacts of the simultaneous switching noise (SSN) in carbon nanotube field effect transistor-based ternary circuits are investigated. These effects, including the peak noise on the <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} </tex-math></inline-formula> and ground rails and the SSN-induced delay and output noise are compared between traditional Cu and multiwall carbon nanotube bundle power interconnects in ternary circuits. Simulations are performed using HSPICE for global power interconnects at 14- and 7-nm technology nodes. The results indicate that for interconnects with 200-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> length, the peak SSN voltage on the <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} </tex-math></inline-formula> and ground rails for a power distribution network, including ten ternary buffers, using multi-walled carbon nanotube (MWCNT) bundle power interconnects is 53% and 40% lower, respectively, compared to Cu power interconnects in the last stage at the 14-nm node. Also, with scaling down the technology to 7 nm, these improvements increase to 60% and 59%, respectively. Moreover, MWCNT bundle power interconnects reduce the SSN-induced delay at the output of the tenth stage for interconnects with 200-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> length on average by 82% as compared to the Cu interconnects at the 14-nm node. This improvement is 73% for the 7-nm technology node.