A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 6; pp. 1345 - 1356
• Main Authors: Lu, Lu, Yoo, Taegeun, Le, Van Loi, Kim, Tony Tae-Hyoung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-06-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS; Data aware; Degradation; Energy consumption; Leakage currents; low power; Power consumption; Power lines; Random access memory; selective dual split power (SDSP) lines; Sensors; SRAM cells; Static random access memory; static random access memory (SRAM); Transistors; vertical read wordline (RWL)
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2019.2956232

This article presents an 8T static random access memory (SRAM) macro with vertical read wordline (RWL) and selective dual split power (SDSP) lines techniques. The proposed vertical RWL reduces dynamic energy consumption during read operation by charging and discharging only selected read bitlines (RBLs). The data-aware SDSP technique combined with vertical write bitlines enhances both the write margin (WM) and the static noise margin (SNM). A 16-kb SRAM test chip fabricated in 65-nm CMOS technology demonstrates the minimum energy consumption of 0.506 pJ at 0.4 V and the minimum operating voltage of 0.26 V.