A 60-GHz Outphasing Transmitter in 40-nm CMOS
This paper presents the analysis, design, and implementation of a 60-GHz outphasing transmitter in 40-nm bulk CMOS. The 60-GHz outphasing transmitter is optimized for high output power and peak power-added efficiency (PAE) while maintaining sufficient linearity. The chip occupies an active area of 0...
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Published in: | IEEE journal of solid-state circuits Vol. 47; no. 12; pp. 3172 - 3183 |
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Main Authors: | , , |
Format: | Journal Article Conference Proceeding |
Language: | English |
Published: |
New York, NY
IEEE
01-12-2012
Institute of Electrical and Electronics Engineers |
Subjects: | |
Online Access: | Get full text |
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Summary: | This paper presents the analysis, design, and implementation of a 60-GHz outphasing transmitter in 40-nm bulk CMOS. The 60-GHz outphasing transmitter is optimized for high output power and peak power-added efficiency (PAE) while maintaining sufficient linearity. The chip occupies an active area of 0.33 mm 2 and consumes 217 mW from a 1-V supply voltage, delivering 15.6-dBm linear output power with 25% PAE (PA). It achieves a 500-Mb/s 16QAM modulation with 12.5-dBm average output power and 15% average efficiency (PA) at an EVM of -22 dB. Mismatch compensation and phase correction are applied to further improve the average output power and efficiency by about 1.6 dB and 4%, respectively. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2012.2216692 |