A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor

• Published in: IEEE journal of solid-state circuits Vol. 52; no. 1; pp. 64 - 76
• Main Authors: Yong-Jin Lee, Wanyuan Qu, Singh, Shashank, Dae-Yong Kim, Kwang-Ho Kim, Sang-Ho Kim, Jae-Jin Park, Gyu-Hyeong Cho
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Applications programs; CMOS; Coarse-fine control; current-mirror flash analog to digital converter (CMF ADC); digital low drop-out (LDO) regulator; dual loop; Electric potential; linear-regulator; Microprocessors; Mobile communication; Mobile computing; Power transistors; Regulators; shift register control; Shift registers; Transient analysis; Transient performance; Transient response; Voltage control; Voltage drop
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2016.2614308

This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity. In the proposed scheme, the output voltage is coregulated by two loops, namely, the coarse loop and the fine loop. The coarse loop adopts a fast current-mirror flash analog to digital converter and supplies high output current to enhance the transient performance, while the fine loop delivers low output current and helps reduce the voltage ripples and improve the regulation accuracies. Besides, a digital controller is implemented to prevent contentions between the two loops. Fabricated in a 28-nm Samsung CMOS process, the proposed digital LDO achieves maximum load up to 200 mA when the input and the output voltages are 1.1 and 0.9 V, respectively, with a chip area of 0.021 mm 2 . The measured output voltage drop of around 120 mV is observed for a load step of 180 mA.