Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

• Published in: IEEE journal of solid-state circuits Vol. 57; no. 1; pp. 127 - 139
• Main Authors: Rossi, Davide, Conti, Francesco, Eggiman, Manuel, Mauro, Alfio Di, Tagliavini, Giuseppe, Mach, Stefan, Guermandi, Marco, Pullini, Antonio, Loi, Igor, Chen, Jie, Flamand, Eric, Benini, Luca
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Artificial neural networks; Cognitive wake-up unit (CWU); deep neural networks (DNNs); digital signal processor (DSP); Encoding; Energy efficiency; Flexibility; Floating point arithmetic; Indexes; Inference; Internet of Things; Internet of Things (IoT); Machine learning; machine learning (ML); magnetoresistive random access memory (MRAM); Magnetoresistivity; Memory management; near-sensor analytic applications (NSAAs); Nonvolatile memory; Random access memory; RISC-V; Sensors; Static random access memory; System on chip; system on chip (SoC)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2021.3114881

The Internet-of-Things (IoT) requires endnodes with ultra-low-power always-on capability for a long battery lifetime, as well as high performance, energy efficiency, and extreme flexibility to deal with complex and fast-evolving near-sensor analytics algorithms (NSAAs). We present Vega, an IoT endnode system on chip (SoC) capable of scaling from a 1.7-<inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> fully retentive cognitive sleep mode up to 32.2-GOPS (at 49.4 mW) peak performance on NSAAs, including mobile deep neural network (DNN) inference, exploiting 1.6 MB of state-retentive SRAM, and 4 MB of non-volatile magnetoresistive random access memory (MRAM). To meet the performance and flexibility requirements of NSAAs, the SoC features ten RISC-V cores: one core for SoC and IO management and a nine-core cluster supporting multi-precision single instruction multiple data (SIMD) integer and floating-point (FP) computation. Vega achieves the state-of-the-art (SoA)-leading efficiency of 615 GOPS/W on 8-bit INT computation (boosted to 1.3 TOPS/W for 8-bit DNN inference with hardware acceleration). On FP computation, it achieves the SoA-leading efficiency of 79 and 129 GFLOPS/W on 32- and 16-bit FP, respectively. Two programmable machine learning (ML) accelerators boost energy efficiency in cognitive sleep and active states.