Agile All-Digital RF Transceiver Implemented in FPGA

• Published in: IEEE transactions on microwave theory and techniques Vol. 65; no. 11; pp. 4229 - 4240
• Main Authors: Cordeiro, R. F., Prata, Andre, Oliveira, Arnaldo S. R., Vieira, Jose M. N., De Carvalho, N. B.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital transceivers; Analog to digital conversion; Analog to digital converters; Bandwidths; Carrier frequencies; Data transmission; delta–sigma modulation (DSM); Digital to analog conversion; Digital to analog converters; Feasibility studies; Field programmable gate arrays; Modulation; Pulse width modulation; pulsewidth modulation (PWM); Radio frequency; Radio transmitters; Receivers; Receivers & amplifiers; software-defined radio (SDR); Transceivers; Transmitters; Upconversion
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2017.2689739

This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter's performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures.