Incremental Delta-Sigma ADCs: A Tutorial Review

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 12; pp. 4161 - 4173
• Main Authors: Tan, Zhichao, Chen, Chia-Hung, Chae, Youngcheol, Temes, Gabor C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-12-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; Analog to digital converters; Analog-to-digital converter (ADC); chopping; decimation filter; Energy conversion efficiency; energy-efficiency; energy-efficient amplifier; Finite impulse response filters; FIR-DAC; incremental ADC (IADC); incremental delta-sigma (ΔΣ) modulator; integrator slicing; Modulation; negative-R assisted integrator; Quantization (signal); sensor interface; Sensor systems; Signal to noise ratio; Topology; Tutorials
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.3033458

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.