Low-Frequency Noise in Vertically Stacked Si n-Channel Nanosheet FETs

• Published in: IEEE electron device letters Vol. 41; no. 3; pp. 317 - 320
• Main Authors: de Oliveira, Alberto V., Veloso, Anabela, Claeys, Cor, Horiguchi, Naoto, Simoen, Eddy
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Carrier number fluctuations; Flicker; flicker noise; Frequency analysis; Gallium arsenide; gate–all–around; input–referred voltage power spectral density; Logic gates; low–frequency–noise; MOSFET; MOSFETs; Nanosheets; Nanowires; n–channel; oxide trap density; Power spectral density; Scattering; Silicon; silicon device; Variation
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2020.2968093

This manuscript presents a systematic low-frequency noise analysis of inversion-mode vertically stacked silicon n-channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input-referred voltage noise Power Spectral Density at flat-band is lower compared to the data on non-stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility.