Device Design Consideration for Robust SiC VDMOSFET With Self-Aligned Channels Formed by Tilted Implantation

• Published in: IEEE transactions on electron devices Vol. 66; no. 8; pp. 3447 - 3452
• Main Authors: Morikawa, Takahiro, Ishigaki, Takashi, Shima, Akio
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-08-2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Alignment; Channels; Ion implantation; Ions; Lithography; Logic gates; Masks; metal–oxide–semiconductor field-effect transistor (MOSFET); MOSFET; Self alignment; self-aligned; short channel; Silicon carbide; silicon carbide (SiC); Surface treatment; TCAD; Threshold voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2019.2924969

We designed a simple self-aligned process for defining short channels in 3.3-kV SiC mymargin DMOSFETs. We utilized a tilt-angle ion implantation technique in the process, and the channel region was formed with the same mask as the source definition. This process eliminates the complicated process of hard mask etching. The simulation showed that a channel is formed by implantation of <inline-formula> <tex-math notation="LaTeX">\sim 1\times 10^{{13}} </tex-math></inline-formula>/cm 2 and ≤600 keV, and channel length can be modulated by tuning incident angles and energies. When a separate mask is used for body formation, our proposed process is less sensitive to the alignment errors of the two masks. Variations in threshold voltages, ON-state resistance, and blocking voltages are significantly reduced in our process. We also show that the mask for body formation is not necessarily required, and we present a set of implantation parameters for channel and body formation only with the mask for the source.