Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic

• Published in: IEEE embedded systems letters Vol. 13; no. 3; pp. 98 - 101
• Main Authors: Mandal, Sumit K., Ayoub, Raid, Kishinevsky, Micahel, Islam, Mohammad M., Ogras, Umit Y.
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01-09-2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Arbitration; Bursty traffic; Entropy; Load modeling; Mathematical analysis; Microprocessors; Modelling; networks-on-chip; Performance analysis; Queueing analysis; queuing analysis; Servers; Solid modeling; System on chip; Systems-on-chip; Traffic models
• ISSN: 1943-0663; 1943-0671
• DOI: 10.1109/LES.2020.3013003

Networks-on-Chip (NoCs) used in commercial many-core processors typically incorporate priority arbitration. Moreover, they experience bursty traffic due to application workloads. However, most state-of-the-art NoC analytical performance analysis techniques assume fair arbitration and simple traffic models. To address these limitations, we propose an analytical modeling technique for priority-aware NoCs under bursty traffic. Experimental evaluations with synthetic and bursty traffic show that the proposed approach has less than 10% modeling error with respect to cycle-accurate NoC simulator.