CMOS-Compatible Self-Aligned In0.53Ga0.47As MOSFETs With Gate Lengths Down to 30 nm

• Published in: IEEE transactions on electron devices Vol. 61; no. 10; pp. 3399 - 3404
• Main Authors: Majumdar, Amlan, Yanning Sun, Cheng-Wei Cheng, Young-Hee Kim, Rana, Uzma, Martin, Ryan M., Bruce, Robert L., Kuen-Ting Shiu, Yu Zhu, Farmer, Damon B., Hopstaken, Marinus, Joseph, Eric A., de Souza, Joel P., Frank, Martin M., Szu-Lin Cheng, Kobayashi, Masaharu, Duch, Elizabeth A., Sadana, Devendra K., Dae-Gyu Park, Leobandung, Effendi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-10-2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS integrated circuits; Effective mass; Logic gates; MOSFET; R&D; Research & development; Resistance; Transconductance; MOSFETs; III-V FETs
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2014.2335747

We demonstrate self-aligned fully-depleted 20-nm-thick In 0.53 Ga 0.47 As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 Ω/sq, respectively. We demonstrate short-channel MOSFETs with gate lengths L G down to 30 nm, low series resistance R EXT = 375 Ω·μm, and high peak saturation transconductance G MSAT = 1275 μS/μm at L G = 50 nm and drain bias V DS = 0.5 V. We obtain long-channel capacitive inversion thickness TINV = 2.3 nm and effective mobility μ EFF = 650 cm 2 /Vs at sheet carrier density N S = 5 × 10 12 cm -2 . Finally, using a calibrated quasi-ballistic FET model, we argue that for L G ≤ 20 nm, μ EFF ≈ 1000 cm 2 /Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.