Experimental I – V(T) and C – V Analysis of Si Planar p-TFETs on Ultrathin Body
We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude...
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| Published in: | IEEE transactions on electron devices Vol. 63; no. 12; pp. 5036 - 5040 |
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| Main Authors: | , , , , , , , , , , |
| Format: | Journal Article |
| Language: | English |
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IEEE
01-12-2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| Abstract | We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance- voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of Cgs to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance Cgd. This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits. |
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| AbstractList | We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance- voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of Cgs to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance Cgd. This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits. We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance–voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of [Formula Omitted] to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance [Formula Omitted]. This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits. |
| Author | Narimani, Keyvan Chang Liu Gia Vinh Luong Glass, Stefan Fox, Alfred Tiedemann, Andreas T. Qing-Tai Zhao Qinghua Han Wenjie Yu Mantl, Siegfried Xi Wang |
| Author_xml | – sequence: 1 surname: Chang Liu fullname: Chang Liu email: c.liu@fz-juelich.de organization: State Key Lab. of Functional Mater. for Inf., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, Germany – sequence: 2 surname: Qinghua Han fullname: Qinghua Han organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 3 givenname: Stefan surname: Glass fullname: Glass, Stefan organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 4 surname: Gia Vinh Luong fullname: Gia Vinh Luong organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 5 givenname: Keyvan surname: Narimani fullname: Narimani, Keyvan organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 6 givenname: Andreas T. surname: Tiedemann fullname: Tiedemann, Andreas T. organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 7 givenname: Alfred surname: Fox fullname: Fox, Alfred organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 8 surname: Wenjie Yu fullname: Wenjie Yu organization: State Key Lab. of Functional Mater. for Inf., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, Germany – sequence: 9 surname: Xi Wang fullname: Xi Wang email: casan@mail.sim.ac.cn organization: State Key Lab. of Functional Mater. for Inf., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, Germany – sequence: 10 givenname: Siegfried surname: Mantl fullname: Mantl, Siegfried organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany – sequence: 11 surname: Qing-Tai Zhao fullname: Qing-Tai Zhao email: q.zhao@fz-juelich.de organization: Peter-Grunberg-Inst. 9, Forschungszentrum Julich, Julich, Germany |
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| Cites_doi | 10.1109/JPROC.2010.2070470 10.1016/0038-1101(92)90184-E 10.1109/LED.2012.2213573 10.1109/LED.2013.2258652 10.1016/j.sse.2013.01.026 10.1109/LED.2010.2041028 10.1109/LED.2010.2047240 10.1109/LED.2009.2017040 10.1038/nature10679 10.1109/LED.2009.2026296 10.1109/TED.2009.2026516 10.1016/j.sse.2013.02.028 10.1109/TED.2016.2535373 10.1109/LED.2009.2028907 10.1109/IEDM.2013.6724560 10.1109/LED.2012.2212175 10.1016/0038-1101(93)90065-X 10.1109/JEDS.2014.2326622 10.1016/j.sse.2015.08.020 10.1109/JEDS.2014.2377576 |
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| SubjectTerms | Annealing Capacitance Capacitance-voltage characteristics Miller capacitance Si planar tunnel FET TFET Silicides Silicon substrates Silicon-on-insulator SOI (semiconductors) TFET TFETs ultrathin body (UTB) |
| Title | Experimental I – V(T) and C – V Analysis of Si Planar p-TFETs on Ultrathin Body |
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