Enhancement-Mode Recessed Gate and Cascode Gate Junctionless Nanowire With Low-Leakage and High-Drive Current

• Published in: IEEE transactions on electron devices Vol. 65; no. 9; pp. 4004 - 4008
• Main Authors: Wong, Hiu Yung, Braga, Nelson, Mickevicius, R. V.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-09-2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Computer simulation; Contact resistance; Doping; Enhancement mode; junctionless (JL); Logic gates; Low currents; Metal oxide semiconductors; Metals; MOS devices; Nanoscale devices; nanowire; Nanowires; nonequilibrium Green’s function (NEGF); Resistance; TCAD simulation; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2018.2856740

Junctionless (JL) nanowire is a promising candidate for the future technology nodes because it obviates the need for ultrasteep junction formation. However, with high doping (e.g., <inline-formula> <tex-math notation="LaTeX">1\times 10^{20} </tex-math></inline-formula>cm −3 ) for large on-state current (<inline-formula> <tex-math notation="LaTeX">I_{ON} </tex-math></inline-formula>) and low contact resistance, it becomes depletion mode (<inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} <0 </tex-math></inline-formula> V for nMOS and <inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} > 0 </tex-math></inline-formula> V for pMOS). In order to have enhancement-mode device (<inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} > 0 </tex-math></inline-formula> V for nMOS and <inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} < 0 </tex-math></inline-formula> V for pMOS), low doping (e.g., 10 19 cm −3 )is required, resulting in low current and high contact resistance. We propose two structures to alleviate the problem, which allow very high doping (e.g., <inline-formula> <tex-math notation="LaTeX">1.5 \times 10^{20} </tex-math></inline-formula> cm −3 ). The proposed concepts are validated by TCAD simulations using classical and quantum (nonequilibrium Green's function) transport models. The first one is to recess the nanowire under the gate region, resulting in enhancement-mode nMOS with >100% gain in <inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula>. The second one is to have a cascode-/dual-gate structure which can further enhance <inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula>, reduce <inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula> and increase <inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> with equivalent on-state gate length (<inline-formula> <tex-math notation="LaTeX">{L}_{G}) = 5 </tex-math></inline-formula> nm and off-state <inline-formula> <tex-math notation="LaTeX">{L}_{G} = 10 </tex-math></inline-formula> nm and <inline-formula> <tex-math notation="LaTeX">50\times </tex-math></inline-formula> increase in <inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula> ratio. Such ideas are applicable to other JL devices such as FinFET, SOI, and nanosheets.