Nonhysteretic Condition in Negative Capacitance Junctionless FETs
This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric...
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Published in: | IEEE transactions on electron devices Vol. 69; no. 2; pp. 820 - 826 |
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Main Authors: | , , |
Format: | Journal Article |
Language: | English |
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IEEE
01-02-2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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Abstract | This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure the hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77 to 400 K. This approach has been assessed with numerical TCAD simulations. |
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AbstractList | This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure the hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77 to 400 K. This approach has been assessed with numerical TCAD simulations. |
Author | Jazaeri, Farzan Sallese, Jean-Michel Rassekh, Amin |
Author_xml | – sequence: 1 givenname: Amin orcidid: 0000-0002-6219-0458 surname: Rassekh fullname: Rassekh, Amin email: rassekh.amin@gmail.com organization: Electron Device Modeling and Technology Laboratory (EDLAB), École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland – sequence: 2 givenname: Farzan orcidid: 0000-0001-9649-3572 surname: Jazaeri fullname: Jazaeri, Farzan organization: Electron Device Modeling and Technology Laboratory (EDLAB), École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland – sequence: 3 givenname: Jean-Michel orcidid: 0000-0003-2109-909X surname: Sallese fullname: Sallese, Jean-Michel organization: Electron Device Modeling and Technology Laboratory (EDLAB), École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland |
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Cites_doi | 10.1021/nl071804g 10.1017/9781316676899 10.1088/0953-8984/10/2/026 10.1109/LED.2016.2523681 10.1109/TED.2019.2944193 10.1016/j.nanoen.2020.104733 10.1109/TED.2015.2465149 10.1109/TED.2011.2156413 10.1109/TED.2013.2261073 10.1109/LED.2016.2628349 10.1063/1.3079411 10.1080/14786444908561372 10.1109/JEDS.2019.2897286 10.1016/j.sse.2016.09.001 10.1080/02564602.2019.1642149 10.1109/TED.2007.911034 10.1038/s41586-018-0854-z 10.1109/JEDS.2020.3020976 10.1007/s10825-020-01475-9 |
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References | ref13 ref12 ref23 Ginzburg (ref8) 1946; 10 ref15 ref14 ref20 ref11 ref22 ref10 ref21 ref2 ref1 ref17 ref16 ref19 ref18 ref9 Salvatore (ref4) 2008 ref3 ref6 Landau (ref7) 1937; 11 Rusu (ref5) 2010 |
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Snippet | This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical... |
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SubjectTerms | Capacitance Charge-based model double-gate junctionless field-effect transistor (DG JLFET) Ferroelectric materials Ferroelectricity Field effect transistors Hysteresis hysteresis free instability Logic gates Mathematical models negative capacitance (NC) Numerical models Semiconductor devices Stability analysis Thickness Voltage |
Title | Nonhysteretic Condition in Negative Capacitance Junctionless FETs |
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