Nonhysteretic Condition in Negative Capacitance Junctionless FETs

• Published in: IEEE transactions on electron devices Vol. 69; no. 2; pp. 820 - 826
• Main Authors: Rassekh, Amin, Jazaeri, Farzan, Sallese, Jean-Michel
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-02-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Charge-based model; double-gate junctionless field-effect transistor (DG JLFET); Ferroelectric materials; Ferroelectricity; Field effect transistors; Hysteresis; hysteresis free; instability; Logic gates; Mathematical models; negative capacitance (NC); Numerical models; Semiconductor devices; Stability analysis; Thickness; Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2021.3133193

This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure the hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77 to 400 K. This approach has been assessed with numerical TCAD simulations.