Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

• Published in: IEEE transactions on nuclear science Vol. 68; no. 5; pp. 611 - 616
• Main Authors: Muthuseenu, K., Barnaby, H. J., Galloway, K. F., Koziukov, A. E., Maksimenko, T. A., Vyrostkov, M. Y., Bu-Khasan, K. B., Kalashnikova, A. A., Privat, A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Electric fields; Field effect transistors; Heavy ion; Heavy ions; Ions; Logic gates; Metal oxide semiconductors; MOSFET; MOSFETs; power MOSFET; Semiconductor devices; Semiconductor process modeling; Silicon; single-event gate rupture (SEGR); super-junction (SJ); technology computer-aided design (TCAD) analysis; Tolerances; Transient analysis; VDMOS
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2021.3053168

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.