The Intel® Programmable and Integrated Unified Memory Architecture (PIUMA) Graph Analytics Processor

• Published in: IEEE MICRO Vol. 43; no. 5; pp. 1 - 11
• Main Authors: Aananthakrishnan, Sriram, Abedin, Shamsul, Cave, Vincent, Checconi, Fabio, Du Bois, Kristof, Eyerman, Stijn, Fryman, Joshua B., Heirman, Wim, Howard, Jason, Hur, Ibrahim, Jain, Samkit, Landowski, Marek M., Ma, Kevin, Nelson, Jarrod, Pawlowski, Robert, Petrini, Fabrizio, Szkoda, Sebastian, Tayal, Sanjaya, Tithi, Jesmin Jahan, Vandriessche, Yves
• Format: Journal Article
• Language: English
• Published: Los Alamitos IEEE 01-09-2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth; Computer architecture; Engines; Instruction sets; Memory management; Microprocessors; Optical interconnects; Prefetching; Single-photon avalanche diodes; Synchronization
• ISSN: 0272-1732; 1937-4143
• DOI: 10.1109/MM.2023.3295848

High performance large scale graph analytics are essential to timely analyze relationships in big data sets. Conventional processor architectures suffer from inefficient resource usage and bad scaling on those workloads. To enable efficient and scalable graph analysis, Intel ® developed the Programmable Integrated Unified Memory Architecture (PIUMA) as a part of the DARPA Hierarchical Identify Verify Exploit (HIVE) program. PIUMA consists of many multi-threaded cores, fine-grained memory and network accesses, a globally shared address space, powerful offload engines and a tightly integrated optical interconnection network. This paper presents the PIUMA architecture, and documents our experience in designing and building a prototype chip and its bring-up process. PIUMA silicon has successfully powered on demonstrating key aspects of the architecture, some of which will be incorporated into future Intel products.