A Secure Phase-Encrypted IEEE 802.15.4 Transceiver Design

• Published in: IEEE transactions on computers Vol. 66; no. 8; pp. 1421 - 1427
• Main Authors: Nain, Ajay Kumar, Bandaru, Jagadish, Zubair, Mohammed Abdullah, Pachamuthu, Rajalakshmi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-08-2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Attacks in wireless networks; Ciphers; Complexity; Computer simulation; Cryptography; Cybersecurity; Depletion; Encryption; energy depletion attack; Hardware; hardware encryption; IEEE 802.15 Standard; IEEE 802.15.4 transceiver; Internet of Things; Nodes; phase encryption; Physical layer; physical layer encryption; physical layer security; Power consumption; security in internet of things; traffic analysis attack; Transceivers
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2017.2672752

With the proliferation of Internet of Things (IoT), the IEEE 802.15.4 physical layer is becoming increasingly popular due to its low power consumption. However, secure data communication over the network is a challenging issue because vulnerabilities in the existing security primitives lead to several attacks. The mitigation of these attacks separately adds significant computing burden on the legitimate node. In this paper, we propose a secure IEEE 802.15.4 transceiver design that mitigates multiple attacks simultaneously by using a physical layer encryption approach that reduces the computations at the upper layers. In addition to providing confidentiality and integrity services, the proposed transceiver provides sufficient complexity to various attacks, such as cryptanalysis and traffic analysis attacks. It also significantly improves the lifetime of the node in the presence of a ghost attacker by preventing the legitimate node from processing the bogus messages and hence combats against energy depletion attacks. The simulation results show that a high symbol error rate at the adversary can be achieved using the proposed transceiver without affecting the throughput at the legitimate node. In this paper, we also analyze the hardware complexity by developing an FPGA and ASIC prototype of the proposed transceiver.