Modeling the I-V characteristics of fully depleted submicrometer SOI MOSFET's

• Published in: IEEE electron device letters Vol. 15; no. 2; pp. 45 - 47
• Main Authors: Hsiao, T.C., Kistler, N.A., Woo, J.C.S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-02-1994; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Capacitance; Conductivity; Electrical resistance measurement; Electronics; Exact sciences and technology; Intrusion detection; MOSFET circuits; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon on insulator technology; Thin film devices; Threshold voltage; Transistors; Silicon on insulator technology; Field effect transistor; Depletion mode; Experimental test; Voltage current curve; Electrical properties; Theoretical study; MOS transistor; Thin film transistor; Modeling
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/55.285378

An analytic current-voltage model for submicrometer fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is presented. This model takes into account the source/drain series resistances which can be especially high in thin film SOI devices. The effect of drain induced conductivity enhancement is also included, which is important for submicrometer channels. The model is verified by comparison to measured SOI I-V characteristics. Good agreement is obtained for SOI film thicknesses ranging from 40 to 220 nm and effective channel lengths down to 0.25 μm.