Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS

• Published in: IEEE photonics journal Vol. 16; no. 5; pp. 1 - 9
• Main Authors: Zhang, Qirui, Zachmann, Isaac, Ji, Lianhua, Mao, Chongchang
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01-10-2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Backplanes; Buffers; Circuits; Decoders; Display devices; Dynamic random access memory; Electrodes; Frame buffer pixel circuit; Gray scale; high pixel per inch (PPI); Image contrast; Image resolution; Liquid crystal on silicon; liquid crystal on silicon (LCOS); Liquid crystals; Memory management; Metal oxide semiconductors; micro-display; Optical memory (data storage); Phase modulation; Pixels; Polarization; Silicon; Voltage
• ISSN: 1943-0655; 1943-0647
• DOI: 10.1109/JPHOT.2024.3462889

This project aims to develop novel frame buffer pixel circuit-based silicon backplanes using 180 nm process technology for polarization-independent liquid crystal on silicon (PI-LCOS) phase modulators. Three unique pixel circuits, which exclusively utilize NMOS transistors, have been designed to minimize pixel size and improve production yield. Additionally, the "Voltage Booster" (VBOOST) technique extends the dynamic voltage range, crucial for stable phase modulation and high grayscale. Efforts are also underway to enhance stability against voltage fluctuation by incorporating the auxiliary capacitor or refined active-driving pixel-electrode stage. The prototype silicon backplane features a 64 × 64-pixel matrix with column and row decoders for individual pixel addressing, facilitating optical testing. By employing a two-stage analog dynamic random-access memory (DRAM), the pixel circuit supports sequential data loading row by row throughout the array while simultaneously displaying previously loaded frame data. This 'frame-at-a-time' data refresh capability is vital for displaying images with full contrast, which is particularly advantageous for holographic and color sequential display applications. Simulation and experimental assessments on the silicon backplane chips demonstrate that these pixel circuits can support a high-resolution LCOS device with approximately 4.15 um x 4.15 um pixel pitch in the 180 nm process technology, a high voltage holding ratio exceeding 94%, and substantial grayscale modulation depth.