A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

• Published in: IEEE journal of solid-state circuits Vol. 47; no. 8; pp. 1828 - 1841
• Main Authors: Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-08-2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptation; Applied sciences; Backplanes; Calibration; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clocks; CMOS; Computer architecture; Decision feedback equalizers; Design. Technologies. Operation analysis. Testing; DFE; Drift; duty cycle correction; dynamic adaptation; Dynamics; Electric potential; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; FFE; Integrated circuits; Linearity; phase rotator linearity; Power electronics, power supplies; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; serial links; Timing; Transceivers; Voltage; Phase rotator; Serial transmission; DFE; FFE; Backplane; phase rotator linearity; Driver; Receiver; Power supply; Decision feedback equalizers; Power electronics; Signalling; Phase locked loop; Transceiver; Silicon on insulator technology; duty cycle correction; serial links; dynamic adaptation; Complementary MOS technology; Ecological approach; Design for environment
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2196313

This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16 GFC and consumes 385 m W/link.