Characteristics of trench j-MOS power transistors

• Published in: IEEE electron device letters Vol. 10; no. 8; pp. 380 - 382
• Main Authors: MacIver, B.A., Valeri, S.J., Jain, K.C., Erskine, J.C., Rossen, R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-08-1989; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Delay; Diodes; Electronics; Etching; Exact sciences and technology; Fabrication; FETs; Other multijunction devices. Power transistors. Thyristors; P-n junctions; Power transistors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon on insulator technology; Substrates; Voltage; Field effect transistor; Silicon; MOS transistor; Voltage current curve; Switching conditions; Power transistor
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/55.31763

The fabrication of trench j-MOS transistors in bulk silicon, so that they can be operated in either a three-terminal or a four-terminal mode, is presented. When the transistors are operated in accumulation mode, the specific on-resistance is 0.8 m Omega -cm/sup 2/. In the four-terminal mode a high transconductance, 290 S/cm/sup 2/, is achieved by manipulating the inversion layer charge. In the three-terminal mode, mixed pentode-triode drain characteristics are exhibited. Response times are comparable to those of a junction FET. These properties make the trench j-MOS transistor attractive for power switching.< >