A Low Voltage 14-Bit Self-Calibrated CMOS DAC with Enhanced Dynamic Linearity

• Published in: Analog integrated circuits and signal processing Vol. 43; no. 2; pp. 137 - 145
• Main Authors: Saeedi, S., Mehrmanesh, S., Atarodi, M.
• Format: Journal Article
• Language: English
• Published: 01-05-2005
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-005-6787-0

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18 u CMOS technology.