A new CR-delay circuit technology for high-density and high-speed DRAMs

• Published in: IEEE journal of solid-state circuits Vol. 24; no. 4; pp. 905 - 910
• Main Authors: Watanabe, Y., Ohsawa, T., Sakurai, K., Furuyama, T.
• Format: Journal Article
• Language: English
• Published: IEEE 01-08-1989
• Subjects: Capacitance; Chromium; Circuit noise; Delay effects; DRAM chips; Noise generators; Power generation; Power supplies; Random access memory; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.34069

The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved.< >