Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise

• Published in: Analog integrated circuits and signal processing Vol. 118; no. 3; pp. 399 - 413
• Main Authors: Raja, M. Ramkumar, Naveen, R., Durai, C. Anand Deva, Usman, Mohammed, Shukla, Neeraj Kumar, Muqeet, Mohammed Abdul
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-03-2024; Springer Nature B.V
• Subjects: Adaptive filters; Adding circuits; Algorithms; Circuits and Systems; Digital filters; Electrical Engineering; Energy efficiency; Engineering; Error reduction; Filter design (mathematics); Filters; FIR filters; Frequency response; Impulse response; Large scale integration; Multipliers; Nodes; Noise reduction; Signal processing; Signal,Image and Speech Processing; Very large scale integration; Ternary multiplier; Carry prediction; All pass transformation; Approximate multiplier; Approximate adder; Sandpiper optimization; Variable digital filter
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-023-02201-8

Variable digital filter (VDF) plays a significant role in communication and signal processing field. Any prototype filter's preferred frequency response is attained by creating All Pass Transformation (APT) based filter to maintain complete control over the cut-off frequency. However, the speed, power, and area usage of the digital filter are constrained by its performance. Therefore, in this manuscript, All Pass Transformation based Variable digital filters (APT-VDF) using Error Reduced Carry Prediction Approximate Adder (ERCPAA) andSandpiper Optimization fostered Approximate Multiplier (SO-AM) is proposed. The proposed APT-VDF-ERCPAA-SOAM filter design is utilized for enhancing the filter efficiency by reducing noise in the sensor nodes. The proposed ERCPAA design is incorporated with carry prediction and constant truncation for diminishing the path delay and area utilization. Moreover, the proposed SO-AM is used for minimizing the design complexity and power utilization. The simulation of the proposed method is activated in Verilog and the design is synthesized in FPGA uses Xilinx ISE 14.5. The proposed APT-VDF- ERCPAA- SO-AM filter design has attained 35.6%, 21.75%, 28.69% lower power and 46.58%, 12.3%, 38.07% lower delay than the existing approaches, like Very Large-Scale Integration design of All Pass Transformation based Variable digital filters uses a new variable block sized ternary adder (VBSTA) and ternary multiplier (APTVDF-VBSTA-TM), Finite Impulse Response (FIR) adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture (FIR- CSDABR-DA) and digital FIR filter design using Carry Save Adder (CSA) and Structured Tree Multiplier (FIR-CSA-STM) respectively.