A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18- \mu m CMOS

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 2; pp. 316 - 325
• Main Authors: Kulej, Tomasz, Khateb, Fabian, Ferreira, Luis H. C.
• Format: Journal Article
• Language: English
• Published: IEEE 01-02-2019
• Subjects: Asynchronous delta–sigma modulator (ADSM); bulk driven (BD); Delay effects; delta–sigma modulator (DSM); Distortion; Gain; low power; low voltage; Modulation; sub-05-V circuits; Threshold voltage; Transistors; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2878625

A new solution for an ultralow-voltage bulk-driven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with <inline-formula> <tex-math notation="LaTeX">V_{\mathrm{ DD}} = 0.3 </tex-math></inline-formula> V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.