Plastic packaging and burn-in effects on ionizing dose response in CMOS microcircuits

• Published in: IEEE transactions on nuclear science Vol. 42; no. 6; pp. 1607 - 1614
• Main Authors: Clark, S.D., Bings, J.P., Maber, M.C., Williams, M.K., Alexander, D.R., Pease, R.L.
• Format: Journal Article
• Language: English
• Published: IEEE 01-12-1995
• Subjects: Assembly; Ceramics; Circuit testing; Costs; Cranes; Degradation; Plastic packaging; Semiconductor device packaging; Temperature; Thermal stresses
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/23.488756

Results are reported from an investigation of the effects of packaging and burn-in on the post-irradiation performance of National Semiconductor 54AC02 Quad 2-input NOR gates. The test population was drawn from a single wafer fabricated in the National process qualified under Mil-Prf-38535 to an ionizing radiation hardness of 100 krads(Si). The test sample was divided between plastic and ceramic packages. Additionally, half of the plastic samples and half of the ceramic samples received a 168 hour/125/spl deg/C burn-in, Two irradiation schemes were used. The first followed Mil-Std-883 Method 1019.4 (dose rate=50 rads(Si)/s). The second used a low dose rate (0.1 rads(Si)/s). AC, DC, transfer function and functional behavior were monitored throughout the tests. Significant differences among the package types and burn-in variations were noted with the plastic, burned-in components demonstrating enhanced degradation. They show the worst post-irradiation parameter values as well as very broad post-irradiation parameter distributions. Degradation is highly dependent upon dose rate and anneal conditions. Two different radiation induced leakage paths have been identified, and their characteristics have been correlated to variations in high dose rate and low dose rate circuit performance. Caution is recommended for system developers to ensure that radiation hardness characterization is performed for the same package/burn-in configuration to be used in the system.