Modeling Power Consumption of NAND Flash Memories Using FlashPower

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 32; no. 7; pp. 1031 - 1044
• Main Authors: Mohan, V., Bunker, T., Grupp, L., Gurumurthi, S., Stan, M. R., Swanson, S.
• Format: Journal Article
• Language: English
• Published: IEEE 01-07-2013
• Subjects: Analytical models; Ash; Capacitance; Computer architecture; Logic gates; Microprocessors; NAND Flash memory; power; Threshold voltage; Transistors
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2013.2249557

Flash is the most popular solid-state memory technology used today. A range of consumer electronics products, such as cell-phones and music players, use flash memory for storage and flash memory is increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and servers. There is a rich microarchitectural design space for flash memory, and there are several architectural options for incorporating flash into the memory hierarchy. Exploring this design space requires detailed insights into the power characteristics of flash memory. In this paper, we present FlashPower, a detailed power model for the two most popular variants of NAND flash, namely, the single-level cell (SLC) and 2-bit Multi-Level Cell (MLC) based flash memory chips. FlashPower is built on top of CACTI, a widely used tool in the architecture community for studying various memory organizations. FlashPower takes several parameters like the device technology, microarchitectural layout, bias voltages and workload parameters as input to estimate the power consumption of a flash chip during its various operating modes. We validate FlashPower against chip power measurements from several different manufacturers and show that our results are comparable to the actual chip measurements. We illustrate the versatility of the tool in a design space exploration of power optimal flash memory array configurations.