A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET

• Published in: IEEE journal of solid-state circuits Vol. 52; no. 7; pp. 1783 - 1797
• Main Authors: Erett, Marc, Hudner, James, Carey, Declan, Casey, Ronan, Geary, Kevin, Hearne, Kay, Neto, Pedro, Mallard, Thomas, Sooden, Vikas, Smyth, Mark, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Wenfeng Zhang, Winson Lin, Xu, Bruce, Chang, Ken
• Format: Journal Article
• Language: English
• Published: IEEE 01-07-2017
• Subjects: Capacitors; clocks; Coils; decision feedback equalizers; field programmable gate arrays; gain; Gain control; Mathematical model; Protocols; receivers; Resistors; Transceivers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2017.2702711

This paper presents a flexible-reach 0.5-16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a multitude of combinations of data-rates and standards such as 10 G-KR, PCIe Gen3/4, and SFP+ across a wide range of channel loss profiles. High-performance techniques employed include a fully adaptive continuous-time linear equalizer, automatic gain control, an 11-tap decision feedback equalizer, wideband LC phase-locked loops, and a high-tracking-bandwidth clock and data recovery loop with low latency. Low-power techniques such as half-rate clocking, active inductors and data-rate programmability are employed to meet stringent power budgets at the different rates. At 16.3 Gb/s, the receiver has a jitter tolerance of >0.3UI at 100 MHz. The transceiver achieves a bit error rate <; 10e - 15 with up to 28-dB loss at Nyquist. It consumes 219 mW/channel at 16.3 Gb/s. The design has robust performance across process, voltage, and temperature, and the architecture allows for a high degree of tuning to handle different system environments in deployment.