Contact Chains for FinFET Technology Characterization

• Published in: IEEE transactions on semiconductor manufacturing Vol. 28; no. 3; pp. 205 - 212
• Main Authors: Brozek, Tomasz, Lam, Stephen, Yu, Shia, Pak, Mike K., Liu, Tom, Vallishayee, Rakesh, Yokoyama, Nobuharu
• Format: Journal Article
• Language: English
• Published: IEEE 01-08-2015
• Subjects: Characterization; CMOS; Contacts; Epitaxial growth; Failure Mode; FinFET; FinFETs; Junctions; Logic gates; Resistance; Semiconductor device measurement; Test Structures; test structures; CMOS; failure mode; characterization; contacts; FinFET
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2015.2451636

Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3-D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes a new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g., bad transistor with very high threshold voltage) a series of measurement under various test conditions was performed and analysed. In order to overcome a limitation of the contact chain size and enable data collection from larger sample of contacts, we proposed to implement the gated chains in addressable arrays, increasing their density and failure rate observability. Finally, the paper presents the examples of electrical failure modes detected by those chains in FinFET process.