A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 31; no. 12; pp. 1950 - 1959
• Main Authors: Safiallah, Mahyar, Danesh, Ahmad Reza, Pu, Haoran, Heydari, Payam
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-12-2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Auto-zero (AZ) amplifier; auto-zero technique; Capacitors; Cascode devices; dc-offset cancellation; Differential amplifiers; Feedback loops; LF noise; Logic gates; Low-frequency noise; Manganese; MOSFET; Stability; Voltage
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2023.3311794

This article presents a current-adjusting auto-zeroing (CAAZ) scheme that overcomes the critical shortcomings of state-of-the-art auto-zero-based offset and low-frequency noise cancellation methods. The proposed technique appropriately adjusts the bias current of individual branches within the amplifier to cancel dc offset and low-frequency noise. The CAAZ method does not suffer from thermal-noise increase due to input signal division and stability issues encountered in input auto-zero (IAZ) or limited allowable gain and input swing experienced in the output auto-zero (OAZ) method. Moreover, it does not create any feedback loop during its operation phases and, thus, does not impose additional stability restrictions on the amplifier within which it is being used. Two differential amplifiers, a single-stage differential amplifier (SSDA) and a folded-cascode amplifier (FCA), employing the proposed CAAZ technique, are designed and simulated in a standard 180-nm CMOS process. Simulation results verify the higher performance of the proposed CAAZ compared to the conventional counterparts.