Comparative analysis of double gate FinFET configurations for analog circuit design

• Published in: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 809 - 812
• Main Authors: Ghai, Dhruva, Mohanty, Saraju P., Thakral, Garima
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2013
• Subjects: Analog circuits; CMOS integrated circuits; FinFETs; Logic gates; Threshold voltage
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2013.6674772

FinFETs are being adopted as an alternative to nanoscale classical MOSFET for digital circuits. The double-gate (DG) FinFET gives rise to a rich design space using various configurations of the gates. Existing research study the DG FinFET for digital design. However, the effectiveness of the various DG FinFET configurations for the analog design has not received much attention. In this paper, we compare the DG FinFET parameters including transconductance (g m ), output resistance (r 0 ), open-circuit gain (g m × r 0 ), transition frequency (f T ) including the most important issue, "nanoscale variability", which are important for analog design. The following three configurations for a fully depleted SOI DG FinFET are analyzed: shorted-gate, independent-gate, and low-power, for both strong inversion and subthreshold operations. Using the results obtained, we present guidelines for DG FinFET based analog design.