Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs

• Published in: IEEE transactions on electron devices Vol. 69; no. 9; pp. 4815 - 4820
• Main Authors: Maniyar, Ashraf, Srinivas, P. S. T. N., Tiwari, Pramod Kumar, Chang-Liao, Kuei-Shu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-09-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Fabrication; Gallium arsenide; gate induced drain leakage (GIDL); Inclination angle; Leakage; Logic gates; MOSFET; MOSFETs; Nanowires; Passivation; Silicon; Tin; Trapezoidal channels; trapezoidal cross section; Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3194109

The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°.