Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation

• Published in: IEEE journal of solid-state circuits Vol. 59; no. 8; pp. 2694 - 2705
• Main Authors: Kim, Sangjin, Um, Soyeon, Jo, Wooyoung, Lee, Jingu, Ha, Sangwoo, Li, Zhiyong, Yoo, Hoi-Jun
• Format: Journal Article
• Language: English
• Published: IEEE 01-08-2024
• Subjects: Capacitors; Computer architecture; Costs; Deep learning; embedded dynamic random access memory (eDRAM); Energy efficiency; Hardware; in-memory computing (IMC); Microprocessors; Sensors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3362699

This article presents Scaling-computing-in-memory (CIM), an energy-efficient embedded dynamic random access memory (eDRAM)-based in-memory-computing (IMC) accelerator with a dynamic-scaling readout for signal-to-quantization-noise ratio (SQNR) boosting and analog-to-digital converter (ADC) overhead reduction. It greatly saves the ADC cost by reducing the required number of ADC-bit and ADC operations by codesigning the algorithm and hardware. Scaling-CIM proposes three key features: 1) dynamic scaling ADC (DSA) boosts SQNR of multibit operation even with low-bit ADC; 2) adaptive analog bit-parallel (AABP) accumulation reduces the redundant ADC operation; and 3) layer-wise adaptive bit-truncation (LABT) search further enhances efficiency on benchmarks. The Scaling-CIM is fabricated in 28-nm CMOS technology and occupies a 2.03-mm2 die area with an 800-kb eDRAM cell. It achieves 39.7-TOPS/W (8-9 b) energy efficiency on the RestNet-18 benchmark and <inline-formula> <tex-math notation="LaTeX">1.96\times </tex-math></inline-formula> higher efficiency figure of merit (FoM) than the previous IMC-based accelerator.