On-chip linear voltage regulator module (VRM) effect on power distribution network (PDN) noise and jitter at high-speed output buffer

• Published in: IEEE electromagnetic compatibility magazine Vol. 4; no. 2; pp. 108 - 113
• Main Authors: Heegon Kim, Sukjin Kim, Joungho Kim, Changwook Yoon, Achkir, Brice, Jun Fan
• Format: Journal Article Magazine Article
• Language: English
• Published: New York IEEE 01-01-2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitors; Integrated circuit modeling; jitter; Noise; on-chip linear voltage regulator module (VRM); PDN noise; Power distribution; power distribution network (PDN); Semiconductors; Switches; System-on-chip; Transistors; Voltage control
• ISSN: 2162-2264; 2162-2272
• DOI: 10.1109/MEMC.2015.7204062

In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module circuit is introduced and analyzed. The transient response of typical on-chip linear VRM circuit is analyzed in power gating condition. When the on-chip linear VRM circuit is inserted between on-chip PDN and operating high-speed output buffers, the on-chip PDN noise and jitter at output buffer are significantly reduced. The larger on-chip decoupling capacitor leads to the lower PDN noise generated by on-chip linear VRM circuit. The on-chip linear VRM also reduces the impact of the aggressor buffer to the victim buffer in different PDN, resulting in the improved performance of the victim buffer. Reduction of PDN noise and jitter at output buffer using on-chip linear VRM are validated based on SPICE simulation with 110 nm CMOS technology library.