Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

• Published in: 2016 IEEE International Electron Devices Meeting (IEDM) pp. 28.2.1 - 28.2.4
• Main Authors: Bardon, M. Garcia, Sherazi, Y., Schuddinck, P., Jang, D., Yakimets, D., Debacker, P., Baert, R., Mertens, H., Badaroglu, M., Mocuta, A., Horiguchi, N., Mocuta, D., Raghavan, P., Ryckaert, J., Spessot, A., Verkest, D., Steegen, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2016
• Subjects: Capacitance; Doping; FinFETs; Layout; Logic gates; Wires
• ISSN: 2156-017X
• DOI: 10.1109/IEDM.2016.7838497

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.