Controlled integration of InP nanoislands with CMOS-compatible Si using nanoheteroepitaxy approach

• Published in: Materials science in semiconductor processing Vol. 182; p. 108585
• Main Authors: Kamath, Anagha, Ryzhak, Diana, Rodrigues, Adriana, Kafi, Navid, Golz, Christian, Spirito, Davide, Skibitzki, Oliver, Persichetti, Luca, Schmidbauer, Martin, Hatami, Fariba
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01-11-2024
• Subjects: CMOS technology; Indium phosphide; Nanoheteroepitaxy; Optoelectronics; Silicon nanotips; CMOS technology; Optoelectronics; Silicon nanotips; Indium phosphide; Nanoheteroepitaxy
• ISSN: 1369-8001; 1873-4081
• DOI: 10.1016/j.mssp.2024.108585

Indium phosphide (InP) nanoislands are grown on pre-patterned Silicon (001) nanotip substrate using gas-source molecular-beam epitaxy via nanoheteroepitaxy approach. The study explores the critical role of growth temperature in achieving selectivity, governed by diffusion length. Our study reveals that temperatures of about 480 °C and lower, lead to parasitic growth, while temperatures about 540 °C with an indium growth rate of about 0.7 Å.s−1 and phosphine flux of 4 sccm inhibit selective growth. The establishment of an optimal temperature window for selective InP growth is demonstrated for a temperature range of 490 °C to 530 °C. Comprehensive structural and optical analyses using atomic force microscopy, Raman spectroscopy, x-ray diffraction, and photoluminescence confirm a zincblende structure of indium phosphide with fully relaxed islands. These results demonstrate the capability to precisely tailor the position of InP nanoislands through a noncatalytic nanoheteroepitaxy approach, marking a crucial advancement in integrating InP nanoisland arrays on silicon devices.