Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for Neurocomputing

We propose an extremely dense, energy-efficient mixed-signal vector-by-matrix-multiplication (VMM) circuits based on the existing 3D-NAND flash memory blocks, without any need for their modification. Such compatibility is achieved using time-domain-encoded VMM design. We have performed rigorous simu...

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Bibliographic Details
Published in:	2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 696 - 701
Main Authors:	Bavandpour, Mohammad, Sahay, Shubham, Mahmoodi, Mohammad Reza, Strukov, Dmitri
Format:	Conference Proceeding
Language:	English
Published:	EDAA 01-03-2020
Subjects:	3D-NAND flash memory Artificial intelligence Automation Discrete wavelet transforms Europe Flash memories Mixed-signal VMM Time domain encoding scheme Time-domain analysis Virtual machine monitors
Online Access:	Get full text
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Summary:	We propose an extremely dense, energy-efficient mixed-signal vector-by-matrix-multiplication (VMM) circuits based on the existing 3D-NAND flash memory blocks, without any need for their modification. Such compatibility is achieved using time-domain-encoded VMM design. We have performed rigorous simulations of such a circuit, taking into account non-idealities such as drain-induced barrier lowering, capacitive coupling, charge injection, parasitics, process variations, and noise. Our results, for example, show that the 4-bit VMM of 200-element vectors, using the commercially available 64-layer gate-all-around macaroni-type 3D-NAND memory blocks designed in the 55-nm technology node, may provide an unprecedented area efficiency of 0.14 pm 2 /byte and energy efficiency of ~11 fJ/Op, including the input/output and other peripheral circuitry overheads.
ISSN:	1558-1101
DOI:	10.23919/DATE48585.2020.9116401