Decoder architecture for array-code-based LDPC codes

Decoder architecture for array-code-based LDPC codes

We describe a decoder architecture intended for decoding array-code-based low-density parity-check (LDPC) codes using the sum-product algorithm (SPA). The advantages of the proposed architecture, as compared to the fully parallel implementation of the SPA, are: reduced memory size, avoidance of comp...

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Bibliographic Details
Published in:GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489) Vol. 4; pp. 2046 - 2050 vol.4
Main Author: Olcer, S.
Format: Conference Proceeding
Language:English
Published: IEEE 2003
Subjects:
Additive white noise
AWGN
Computer architecture
Concurrent computing
Iterative decoding
Laboratories
Parallel architectures
Parity check codes
Processor scheduling
Sum product algorithm
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Description
Summary:We describe a decoder architecture intended for decoding array-code-based low-density parity-check (LDPC) codes using the sum-product algorithm (SPA). The advantages of the proposed architecture, as compared to the fully parallel implementation of the SPA, are: reduced memory size, avoidance of complex signal interconnect patterns, and ease of programmability to accommodate various code parameters. These advantages are derived from exploiting the well-defined structure of the parity-check matrix of array-code based LDPC codes. Sum-product decoding with modified message-passing schedules are proposed to simplify the decoder implementation further.
ISBN:9780780379749
0780379748
DOI:10.1109/GLOCOM.2003.1258596