Superconducting integrated circuit fabrication with low temperature ECR-based PECVD SiO/sub 2/ dielectric films

• Published in: IEEE transactions on applied superconductivity Vol. 5; no. 2; pp. 2303 - 2309
• Main Authors: Sauvageau, J.E., Burroughs, C.J., Booi, P.A.A., Cromar, M.W., Benz, R.P., Koch, J.A.
• Format: Journal Article
• Language: English
• Published: IEEE 01-06-1995
• Subjects: Electrons; Etching; Fabrication; Josephson junctions; Plasma temperature; SQUIDs; Standards development; Superconducting integrated circuits; Very large scale integration; Voltage-controlled oscillators
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/77.403046

A superconducting integrated circuit fabrication process has been developed to encompass a wide range of applications such as Josephson voltage standards, VLSI scale array oscillators, SQUIDs, and kinetic-inductance-based devices. An optimal Josephson junction process requires low temperature processing for all deposition and etching steps. This low temperature process involves an electron cyclotron resonance-based plasma-enhanced chemical vapor deposition of SiO/sub 2/ films for interlayer dielectrics. Experimental design and statistical process control techniques have been used to ensure high quality oxide films. Oxide and niobium etches include endpoint detection and controlled overetch of all films. An overview of the fabrication process is presented.< >