A 320 Gb/s-Throughput Capable 2 \,\times\,2 Silicon-Plasmonic Router Architecture for Optical Interconnects

• Published in: Journal of lightwave technology Vol. 29; no. 21; pp. 3185 - 3195
• Main Authors: Papaioannou, S., Vyrsokinos, K., Tsilipakos, O., Pitilakis, A., Hassan, K., Weeber, J.-C, Markey, L., Dereux, A., Bozhevolnyi, S. I., Miliou, A., Kriezis, E. E., Pleros, N.
• Format: Journal Article
• Language: English
• Published: IEEE 01-11-2011
• Subjects: Couplings; Dielectric-loaded surface plasmon polariton waveguide; Integrated circuit modeling; Optical filters; optical interconnects; Optical resonators; optical routing; Optical switches; Optical waveguides; Plasmons; racetrack/ring resonator; silicon multiplexer; silicon-on-insulator; thermo-optic switching
• ISSN: 0733-8724; 1558-2213
• DOI: 10.1109/JLT.2011.2167315

We demonstrate a 2 × 2 silicon-plasmonic router architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final router architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.