False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.
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Published in: | Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002 pp. 566 - 569 |
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Format: | Conference Proceeding |
Language: | English |
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Abstract | We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths. |
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AbstractList | We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths. |
Author | Cheng, Kwang-Ting Krstic, Angela Liou, Jing-Jia Wang, Li-C. |
Author_xml | – sequence: 1 givenname: Jing-Jia surname: Liou fullname: Liou, Jing-Jia organization: University of California, Santa Barbara, CA – sequence: 2 givenname: Angela surname: Krstic fullname: Krstic, Angela organization: University of California, Santa Barbara, CA – sequence: 3 givenname: Li-C. surname: Wang fullname: Wang, Li-C. organization: University of California, Santa Barbara, CA – sequence: 4 givenname: Kwang-Ting surname: Cheng fullname: Cheng, Kwang-Ting organization: University of California, Santa Barbara, CA |
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Keywords | statistical timing analysis critical path selection false path |
Language | English |
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SubjectTerms | Hardware -- Hardware validation |
Title | False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation |
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