False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

• Published in: Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002 pp. 566 - 569
• Main Authors: Liou, Jing-Jia, Krstic, Angela, Wang, Li-C., Cheng, Kwang-Ting
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 10-06-2002
• Series: ACM Conferences
• Subjects: Hardware > Hardware validation; statistical timing analysis; critical path selection; false path
• ISBN: 1581134614; 9781581134612
• ISSN: 0738-100X
• DOI: 10.1145/513918.514061

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.